The present invention relates to a process switch apparatus suitably applied to, for example, a dispatcher of a computer system having a check point recovery function.
A conventional database management system is provided with a process (referred to as a log writer hereinafter) exclusively for writing a history of transaction processing (log) to a disk apparatus or the like. This log writer writes log data, which has been written to a log buffer area secured in a main memory, to the disk apparatus in a response to an instruction from another process or in predetermined timing. In order to maintain the consistency of a database, when the transaction is committed, its commit log has to be written to the disk apparatus. If, therefore, a process under execution of transaction starts a commit processing, it instructs the log writer to write its own commit log to the disk apparatus. In the log writer responds that the commit log has been written to the disk apparatus, the process under execution of transaction completes the commit processing.
Let us consider that the above database management system is operated in a computer system which causes a delay in writing to the disk apparatus until the next check point. These check points are picked up properly in order to allow a processing to be resumed while maintaining the matching of the whole system when the processing is interrupted due to a malfunction, and the states of the system (those of the CPU and main memory) necessary for continuing the processing is recorded for each of the check points.
As illustrated in FIG. 1, when the process under execution of transaction 1(T1) starts a commit processing (1), it instructs a log writer to write its own commit log to a disk apparatus. The log writer issues a command (write) for writing the commit log to the disk apparatus (2). In the computer system, however, the writing to the disk apparatus is delayed (4) until the next check point (3), and the log writer is placed in the writing standby (sleep) state until then.
In this state, when the process under execution of another transaction 2(T2) starts a commit processing (5), even though it instructs the log writer to write a commit log, the reception of the writing is delayed until its preceding writing is finished (6). The writing is also delayed (8) until the next check point (7).
In the computer system described above, the process exclusively used for picking up a check point (hereinafter referred to as a check point process) is executed by a processor to prevent the other processes from being operated during the pickup of the check point. Since the check point process is scheduled by the first priority, the process executed immediately before the check point is interrupted and the check point process starts to be executed. The check point process simply goes around an idle loop and hardly replaces data of a cache while hardware for a cache flash is returning data from a dirty line of the cache to a main memory. Thus, data to which the process executed immediately before the check point accesses, is held as it is in the cache at the end of the check point. However, the process executed immediately before the processing of the check point is completed, is not always prioritized. If another process is executed, neither cached commands nor data can be used, thus increasing in cache miss.
The first problem of the foregoing conventional system is that the process is switched to the log writer fairly prior to the check point. In other words, if the switching of the process is delayed until immediately before the check point, the commit log indicated later can be written to the disk apparatus, together with the commit log indicated earlier, at the next check point, thus improving in throughput.
The second problem is that the process executed immediately before the check point is not prioritized at the time of completion of the check point. In other words, taking into consideration that the check point process hardly replaces data of the cache, a cache miss can greatly be reduced by prioritizing the process executed immediately before the check point.
In a multiprocessor system as disclosed in U.S. Pat. Nos. 5,261,053 and 5,185,861, if the same process as the last process is executed within a predetermined period of time after the last process is executed, the last process is also assigned to the same processor. Since, in this case, no check point process is taken into consideration, the assignment of the process is not effectively controlled immediately after a check point if the time required for the check point process is long.